FPGA Implementation Of Content Addressable Memory
S.Gokila, KIT- KalaignarKarunanidhi Institute of Technology; R.Mythili ,; S.Chandra kala ,
Decoder, Fredkin gate, FPGA, Peres gate, Reversible logic
To reduce the power dissipation in circuits, the reversible logic design is implemented. Reversible logic design is one of the main low power techniques. In the proposed design the address decoder is designed using basic reversible logic gates Fredkin gate and Peres gate.The encoder is designed using Fredkin and Feynman gate. In the use of Peres gate in proposed design reduce the quantum cost and power dissipation of the decoder. The Content Addressable memory architecture will be realized using FPGA
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Paper ID: GRDCF002094
Published in: Conference : International Conference on Innovations in Engineering and Technology (ICIET - 2016)
Page(s): 306 - 311
Published in: Conference : International Conference on Innovations in Engineering and Technology (ICIET - 2016)
Page(s): 306 - 311