A Low Power Memory Architecture for Zigbee Trans-Receiver
M.Marudhupandian, KIT- KalaignarKarunanidhi Institute of Technology; V.Kamalkumar ,
I/O supply voltage, Retention Flip flop, Standby leakage current, Standby mode, Level-Conversion, Dual-Edge triggered flip-flop
A Low-power memory architecture for Zigbee Trans-Receiver is designed in this project. It proposes a level converting Retention flip-flop (RFF) in dual edge triggered pulse with feedback system in Zigbee SoC’s Trans-receiver. This RFF the master flip flop are hold the data in standby mode and the data will be restored in the slave flip flop in active mode thus reduces the power consumption. Then the data will be passed from the VDD, Coreto and VDD, IO with the help of NMOS pass-Transistor. This proposed RFF does not require any additional control signals for power and data transitioning. This RFF with dual-edge triggered pulse with feedback system will overcome the problems like high power consumption, large DC current and low performance when compared with existing single-edge triggered RFF. Using 180nm technology the proposed RFF is designed for low power consumption using Tanner EDA Tool.
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Paper ID: GRDCF002087
Published in: Conference : International Conference on Innovations in Engineering and Technology (ICIET - 2016)
Page(s): 277 - 280
Published in: Conference : International Conference on Innovations in Engineering and Technology (ICIET - 2016)
Page(s): 277 - 280