Speed Optimised CORDIC Based Fast Algorithm for DCT
V.K.Vidhysankari, Dr.Mahalingam College of Engineering and Technology; B.Pradeep Kumar ,
Compression, CORDIC, DCT, Carry Save Adder, Carry Look-ahead Adder, Processing Elements
Discrete Cosine Transform is the most widely used transform recorded in the history especially for image and video compression. DCT can be efficiently carried out using a well-known iterative algorithm called CORDIC to perform vector rotations. An efficient CORDIC based fast algorithm for DCT is presented with some notable advantages like data flow similar to Cooley - Tukey FFT, identical post-scaling factor and rotation angles in arithmetic sequence. CORDIC types are reduced to one by choosing trigonometric formula. This algorithm overcomes the problem of non-synchronization among the CORDIC rotation angles. This is achieved by using Carry Save Adder (CSA) in the Processing Elements (PE) in the place of full adders and the two different PEs are used to exploit four PEs. The delay reduces drastically by using modified 4:2 Carry Save Adder architecture
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[1] Ahemed, N., Nagarajan, T.andRao, K.R. (1974). Discrete Cosine Transform. IEEE Trans. Comput. C-23, 90-94.
[2] Chen, C.T., Chen, L.G.,Chiueh, T.D. and Hsiao,J.H. (1995). High throughput CORDIC-based systolic array design for the discrete cosine transform.IEEE Trans. Circuits Syst. Video Technol. 5 (3), 218-225.
[3] Chen, C.H., Liu, B.D., and Yang, J.F. (2004). Direct recursive structures for computing radix-r two dimensional DCT/IDCT/DST/IDST.IEEE Trans. Circuits Syst.–I: Regul.Pap.51, 10.
[4] Fanucci, L.,Saletti, R. and Saponara, S. (2001). Parameterized and reusable VLSI macro cells for low-powerof 2-D Discrete-Cosine-Transform.Microeletron.J.32, 1035-1045.
[5] Huang, H., andXiao. L., CORDIC based fast algorithm for power-of-two point DCT and its efficient VLSI implementation.Microelectronics J., Vol. 45, Issue 11, 1480-1488, Nov. 2014.
[6] Hou, H.S. (1997). A fast recursive algorithm for computing the discrete cosine transform.IEEE Trans. Acoust. Speech Signal Process.ASSP-35, 1445-1461.
[7] Huang, H., andXiao, L. (2013). Variable length reconfigurable algorithms and architectures for DCT/IDCT based modified unfolded CORDIC.The Open Electrical & Electronic Engineering Journal 7, (Supple 1: M8), 71-81.
[8] Kaddachi, M.L.,Soudani, A.,Lecuire, V., Makkaoui, L.,
Moureaux, J.M. and Torki, K. (2012).Design and performance analysis of a zonal DCT-based image encoder for wireless camera sensor networks.Microelectron.J. 43, 809-817.
[9] Narasimha, M.J., and Peterson, A.M. (1978). On the computation of the discrete cosine transform.IEEE Trans. Commun. 26 (6), 934-936.
[10] Pan, S.B., andPark,R.H. (1997).Unified systolic arrays for computation of DCT/DST/DHT. IEEE Trans. Circuit Syst. Video Technol. 7 (2), 413-419.
[11] RiyaGarg, SumanNehra and B.P. Singh., (Mar. 2013). Low power 4-2 Compressor for Arithmetic Circuits.IJRTE,Vol. 2, Issue 1, ISN: 2277-3878.
[12] Radhakrishnan, D.,Preethy, A.P. (2000). Low Power CMOS Pass Logic 4-2 Compressor for High-Speed Multiplication.Proc. IEEE Midwest Symp. On Circuits and Systems, pp. 1-3.
[13] RiyaGarg, SumanNehra and Singh, B.P. (2013).Low power Full Adder using 9T Structure.International Journal on Recent Trends in Engineering and Technology, Vol. 8, No. 2, pp. 7-10.
[14] RiyaGarg, SumanNehra and Singh, B.P. (2013).A New Design of Full Adder based on XNOR-XOR Circuit.International Journal of Computer Application, Vol. 8, No. 2, pp. 7-10.
Paper ID: GRDCF002062
Published in: Conference : International Conference on Innovations in Engineering and Technology (ICIET - 2016)
Page(s): 443 - 451
Published in: Conference : International Conference on Innovations in Engineering and Technology (ICIET - 2016)
Page(s): 443 - 451